Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism

Test data travels through a System on Chip (SOC) from the chip pins to the Core-Under-Test (CUT) and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented using dedicated communication infrastructure. However, also existing functional interconnect, such as a bus or Network on Chip (NOC), can be reused as TAM; this will reduce the overall design effort and associated silicon area. For a given core, its test set, and maximal bandwidth that the functional interconnect can offer between test equipment and core-under-test, our approach instantiates a test wrapper for the coreunder-test such that the test length is minimized. Unfortunately, it is unavoidable that along with the test data also unused (idle) bits are transported. This paper presents a holistic TAM bandwidth under-utilization analysis when functional interconnect is considered for Responsible Editor: C. Metra This paper is an extended version of a paper published at the IEEE European Test Symposium (ETS), May 25–29, 2008 in Verbania, Italy [28]. A. van den Berg · P. Ren · G. Gaydadjiev · K. Goossens Department of Computer Engineering, Delft University of Technology, Mekelweg 4, 2628CD Delft, The Netherlands G. Gaydadjiev e-mail: [email protected] E. J. Marinissen · K. Goossens Corporate Innovation & Technology, NXP Semiconductors, High Tech Campus 37, 5656AE Eindhoven, The Netherlands test data transportation. We classify the idle bits into four types that refer to the root-cause of bandwidth under-utilization and pinpoint design improvement opportunities. Experimental results show an average bandwidth utilization of 80%, while the remaining 20% is consumed by the idle bits.